A traditional computer memory hierarchy has developed as a consequence of the relative price and performance characteristics of available technologies. The fastest and most expensive memories are constructed from static random access memory chips; those constructed from dynamic access memory chips are somewhat slower, but considerably less expensive. Rotating magnetic media-based memory is dramatically slower than either of the aforementioned semiconductor-based memories, but its speed disadvantage is offset by a much lower cost per megabyte. Magnetic tape storage, which is far slower and considerably less expensive than rotating magnetic media-based memory, is at the bottom of the traditional memory hierarchy.
New technology and refinements of existing technology promise to alter the traditional hierarchy. Already, Bi-CMOS DRAM designs (arrays which incorporate transistors of both bipolar and CMOS varieties) have been announced. This type of DRAM array is expected to eliminate most of the four-fold speed advantage currently held by static random access memories (SRAMs). Additionally, the never-ending quest for faster processing speeds has led to the practice of buffering a large, relatively slow memory with a buffer constructed from relatively fast memory. For example, rather than constructing main memory exclusively from fast, but costly SRAMs, a relatively small, but high-speed SRAM cache memory is used to front-end a large DRAM main memory. Another example is the extensive use of semiconductor memories (either static or dynamic) as input-output buffers for tape drives and disk drives. The main reason for the use of semiconductor buffers in sequentially-accessed storage peripherals is the ability of such buffers to increase system throughput by reducing delays associated with the difference between the speed of the mechanical device and the speed of the system's semiconductor main memory. As optical storage technology becomes more sophisticated and less costly, it will likely begin to supplant sequentially-accessed magnetic storage.
As refinements of semiconductor manufacturing technology have simultaneously reduced the unit cost and increased the density of semiconductor memory, it has been used with increasing frequency in applications that were once the domain of rigid disk drives. In the past, semiconductor storage has quadrupled in capacity (density) roughly every three years, whereas rigid disk drives have only doubled in capacity within the same period. Given those trends, if the price curves for the two technologies are extended into the future, there is a crossover point where semiconductor storage becomes less expensive than rigid disk storage. Various estimates have placed that crossover point anywhere between the mid-1990s and the year 2000.
Semiconductor memory, configured as either a high-speed solid-state device (HSSD) or as a solid-state disk drive (SSDD), is already having an impact on the rigid disk drive market. The main difference between HSSDs and SSDDs is that the HSSD does not emulate a disk drive. In addition, HSSDs interface directly to very high-speed memory buses. Although the SSDD is typically a plug-in and run device, it is limited by the band width of the I/O channel and the overhead associated with emulating a disk drive.
Semiconductor memory configuration is highly application dependent. Certain applications such as design automation, seismic data processing, weather forecasting, scientific simulation, artificial intelligence and graphics imaging and animation require large system memories. Other applications, such as real-time simulation and data acquisition, can just as easily use semiconductor memory configured either as an HSSD or as an SSDD. For example, in data acquisition applications, data is beamed down from satellites to HSSDs that act as temporary storage buffers until the data can be off-loaded to permanent storage on disk or tape.
Because of the increased processor overhead, decreased system speed and additional memory burden associated with error correction, semiconductor chips used in main memory applications must generally be full specification. By full specification, it is meant that the chips are free of hard errors and demonstrate an acceptable soft error rate. Because HSSDs are generally connected to high-speed data buses, implementation of an error-correction system on such a device may also be counterproductive. However, in the case of SSDDs, where speed is already limited by the band width of the I/O channel and disk-drive-emulation overhead, the implementation of an error-correction system will degrade system performance almost imperceptibly.
Although the current cost of an SSDD is a minimum of $700 per megabyte, a number of emerging technologies and new packaging techniques which make complete or partial use of off-spec DRAMs could dramatically reduce the cost. One promising technique is wafer array memory technology, which is an extension of wafer scale integration. With this technology, a stack of wafers is vertically interconnected. Because this approach enables a manufacturer to use standard full-specification DRAMs together with less-than-perfect, "off-spec" DRAMS, production costs are dramatically reduced.
It would be highly desirable to be able to construct an SSDD exclusively from "off-spec" DRAM chips which would normally be considered worthless for main memory applications. Such a capability would dramatically reduce the cost of such an array.